In traditional complementary metal-oxide semiconductor (CMOS) very large scale integration (VLSI) circuit designs, CMOS integrated circuits are powered by one voltage level. Although traditional CMOS integrated circuits powered by one voltage level continue to be developed and manufactured, the demand for longer battery life in many electronic devices, such as ultra low-power microprocessors used in portable computers and digital signal processors used in personal digital assistants and cellular telephones, is creating a demand for CMOS VLSI circuit designs that consume less power than traditional designs.
One approach to reducing power in a CMOS circuit design is to power the CMOS circuits with two voltage levels. The first or higher voltage level powers critical circuit paths and critical functional units. A critical circuit path is a circuit path that is designed to transmit signals as fast as possible along the path. A critical functional unit is a functional unit, such as an arithmetic and logic unit, that is designed perform a logical operation as fast as possible. A CMOS circuit path powered at a higher voltage level transmits a signal more rapidly than the same CMOS path powered at a lower voltage level, and a CMOS functional unit powered by higher voltage level generally processes signals more rapidly than the same functional unit powered at a lower voltage level. The second or lower voltage level powers non-critical paths and non-critical functional units. The result of applying this design approach to CMOS circuits is that the non-critical CMOS circuit paths, which are powered at the lower voltage level, and the non-critical CMOS functional units, which are also powered at the lower voltage level, consume less power than they would consume if powered at a higher voltage level. Thus, a complete CMOS circuit can be designed to consume less power when powered at two voltage levels than when powered at one voltage level.
One problem with powering a CMOS circuit with two voltage levels, such as a lower voltage level and a higher voltage level, is that signals generated by circuits powered at the lower voltage level are usually incompatible with circuits powered at the higher voltage level. To make signals generated by circuits powered at the lower voltage level compatible with circuits powered at the higher voltage level, a voltage level converter is inserted between the circuits powered at the lower voltage level and the circuits powered at the higher voltage level.
FIG. 1 is a schematic diagram of a prior art voltage level converter 100. The prior art voltage level converter 100 includes n-type insulated-gate field-effect transistors (FETs) 102-103, an inverter 104, cross-coupled p-type insulated-gate FETs 106-107, and an output buffer 109. The p-type insulated-gate FET 106 is coupled to the n-type insulated-gate FET 102 at node 111, the p-type insulated-gate FET 107 is coupled to the n-type insulated-gate FET 103 at node 113, the gate of the p-type insulated-gate FET 106 is coupled to the node 113, the gate of the p-type insulated-gate FET 107 is coupled to the node 111, and the input node 115 is coupled to the n-type insulated-gate FET 103 through the inverter 104.
FIG. 2A is a sketch of a logic signal illustrating a transition from a high logic level, VCCL, to a low logic level, VLOW. The logic signal shown in FIG. 2A is one example of INPUT SIGNAL 117 shown in FIG. 1. FIG. 2B is a sketch of the logic signal at the node 113 that results from applying the input logic signal shown in FIG. 2A to the prior art voltage-level converter 100 shown in FIG. 1. FIG. 2C is a sketch of the BUFFERED OUTPUT SIGNAL 127 that results from applying the input logic signal shown in FIG. 2A to the prior art voltage level converter 100.
Referring again to FIG. 1, for INPUT SIGNAL 117 at a high logic level (assuming a high logic level corresponds a positive voltage level) as shown in FIG. 2A at 201, the n-type insulated-gate FET 102 is turned on, the p-type insulated-gate FET 106 is turned off, the n-type insulated-gate FET 103 is turned off, and the p-type insulated-gate FET 107 is turned on. Thus, substantially zero current flows between the power supply node 119 and the ground node 121, substantially zero current flows between the power supply node 123 and the ground node 125, and substantially zero power is consumed by the voltage level converter 100.
FIG. 2D is a sketch of a logic signal illustrating a transition from a low logic level, VLOW, to a high logic level, VCCL. For the INPUT SIGNAL 117 at a low logic level (assuming a low logic level corresponds to a zero voltage level) as shown at 203 in FIG. 2D, the n-type insulated-gate FET 102 is turned off, the p-type insulated-gate FET 106 is turned on, the n-type insulated-gate FET 103 is turned on, and the p-type insulated-gate FET 107 is turned off. Thus, substantially zero current flows between the power supply node 119 and the ground node 121, substantially zero current flows between the power supply node 123 and the ground node 125, and substantially zero power is consumed by the voltage level converter 100. Therefore, for a static input logic signal at input node 115 substantially zero power is consumed by the prior art voltage-level converter 100.
However, during the transition of a signal at the input node 115 power is consumed by the prior art voltage-level converter 100. For example, during the transition of the INPUT SIGNAL 117 from a high logic-level to a low logic-level, as shown at 205 in FIG. 2A, the p-type insulated-gate FET 103 turns on before the n-type insulated-gate FET 107 turns off, so current flows between the power supply node 123 and the ground node 125. Similarly, during the transition of INPUT SIGNAL 117 from a low logic-level to a high logic-level, as shown at 207 in FIG. 2D, the n-type insulated-gate FET 102 turns on before the p-type insulated-gate FET 106 turns off, so current flows between the power supply node 119 and the ground node 121. Therefore, power is consumed by voltage converter circuit 100 during transitions of the INPUT SIGNAL 117.
Unfortunately, including a voltage-level inverter, such as voltage-level converter 100, in a two voltage-level CMOS VLSI circuit design increases the power consumed by the circuit when compared to the power consumed in a traditional CMOS one supply voltage circuit design.
For these and other reasons there is a need for the present invention.